Japanese Patent Laid-Open Publication No. 2011-129816 (Patent Document 1) discloses a memory cell in which a memory gate structure is disposed between two select gate structures (see FIG. 16 in the Patent document 1). The memory cell includes a drain region, to which a bit line is connected, and a source region, to which a source line is connected. Over a memory well, the first select gate structure, the memory gate structure, and the second select gate structure are arranged in this order in a direction towards the source region from the drain region. In the memory cell, the memory gate structure includes a charge storage layer. Data is programmed by injecting charge into the charge storage layer or erased by removing charge from the charge storage layer.
To inject charge into the charge storage layer in the above-described memory cell, a low bit voltage from the bit line is applied to a channel layer below the memory gate structure through the first select gate structure while the second select gate structure, which is connected to the source line, blocks the voltage. At this time, a high memory gate voltage is applied to the memory gate electrode of the memory gate structure. Charge is injected into the charge storage layer by a quantum tunneling effect caused by a voltage difference between the bit voltage and the memory gate voltage.
In a non-volatile semiconductor memory device in which the above-configured memory cells are arranged in a matrix of rows and columns, the memory cells share a memory gate line to which a high memory gate voltage is applied. In a case where a high memory gate voltage is applied to the memory gate line to inject charge into the charge storage layer of one of the memory cells, the high memory gate voltage is applied also to the memory gate electrodes of the remaining memory cells that share the memory gate line although the charge is not supposed to be injected into the charge storage layers of the remaining memory cells.
In the memory cell in which the charge is not supposed to be injected into the charge storage layer, a high bit voltage is applied from the bit line to the channel layer of the memory gate structure through the first select gate structure while the second select gate structure, which is connected to the source line, blocks a voltage to be applied to the channel layer. Thus, in the case where a high memory gate voltage is applied to the memory gate electrode of the memory gate structure, a high bit voltage is applied to the channel layer, making a voltage difference between the memory gate electrode and the channel layer small. As a result, the quantum tunneling effect does not occur and the charge is not injected into the charge storage layer.